1. Field of the Invention
The present invention relates to a semiconductor device for which a communication function has been provided, and in particular to a system LSI chip into which a transmission FIFO buffer has been incorporated.
2. Related Arts
Recently, a number of different data communication protocols have been developed, and a variety of dedicated semiconductor devices have been manufactured to implement these protocols. Incorporated in these semiconductor devices, for example, system LSI chips, are communication macro circuits and, somewhat less frequently, FIFO buffers for storing data to be transmitted are included in the communication macro circuits.
The overall control of a system, which is connected together by a communication macro circuit, is provided by a control unit, such as a micro-controller, which is incorporated into the system LSI. In order to improve the overall performance of the system, a process involving the writing of transmission data in an FIFO buffer must be efficiently performed.
Conventionally, when a transmission FIFO buffer contains no data for transmission, a communication macro circuit transmits a data write request to a micro-controller, which thereafter writes in the FIFO buffer those data which are to be transmitted next.
However, in a large system, a micro-controller performs not only the transmission of data but also a process having a higher priority, such as a timer interrupt process, within a specific time interval. Therefore, the transmission process and the other process having a higher priority may be performed at the same time.
In this case, since the process having a higher priority is performed first, even when a write request from the communication macro circuit has been received, the micro-controller can not write transmission data in the FIFO buffer within a predetermined period of time, so that the FIFO buffer becomes empty and a communication error occurs.
In order to avoid the occurrence of communication errors in a system which performs a large amount of processing, software countermeasures are conventionally employed whereby data are written in an FIFO buffer not only following the reception of a write request from a communication macro circuit, but also periodically, in order to ensure that the FIFO buffer does not become empty.
That is, in addition to a write request output by the communication macro circuit, an interrupt having a very high priority, such as a timer interrupt, is employed to force the micro-controller to write data in the FIFO buffer.
However, in a system for which the amount of processing has been increased, if a communication process is monitored by employing a timer interrupt in addition to a write request output by a communication macro circuit, the software processing will be complicated.
On the contrary, if a timer interrupt is not used and a write request is issued only when an FIFO buffer has become empty, communication errors will occur more frequently in accordance with the increase in the amount of processing which is performed.
As a second problem, a communication protocol, wherein a data format and a communication speed are defined, is employed for the communication of data among the devices, such as an integrated circuit like a microcomputer and a host computer or a periphery device.
Although the communication protocol tends to be complicated and the communication speed tends to be increased, the processing speed of an integrated circuit, which receives or transmits data, can not be increased so that it catches up with the communication speed. Therefore, a buffer, such as an FIFO buffer, is provided for the integrated circuit for the temporary storage of data which are to be transmitted or which are received. The stored data are processed in accordance with the processing speed of the integrated circuit to thus resolve the problem posed by a difference in the communication and the processing speeds
FIGS. 21A to 21C are operational diagrams (I) for conventional data communication. An explanation will now be given for a case where, as is shown in FIG. 21A, an integrated circuit 100, including a CPU 180, a RAM 181 and a buffer 182, exchanges data with a host computer 201 via a communication line 202.
When the integrated circuit 100 receives data from the host computer 201, the data format consists of a data string 101 composed of a number a of bytes of data A, a number b of bytes of data B, and a number c of bytes of data C, as is shown in FIG. 21B. If, as is shown in FIG. 21C, the buffer 182 of the integrated circuit 100 has a memory capacity of (a+b+c) bytes, the entire data string 101 can-be stored temporarily.
The entire data string 101, which is temporarily stored in the buffer 182, is then transmitted to the RAM 181 of the integrated circuit 100, and the data represented by each byte count which is determined in accordance with the communication protocol is interpreted and disposed by software.
FIG. 22 is an operating diagram (II) for conventional data communications for which a plurality of buffers is used. In this example, a plurality of buffers 185, 186 and 187, for which the memory capacity in bytes is defined in accordance with the communication protocol, and a data distribution circuit 189, for counting the bytes of the received data and for distributing the data to buffers having adequate sizes, are provided for an integrated circuit 100. For each set of bytes defined in accordance with the communication protocol, the data distribution circuit 189 assigns a different data writing destination buffer. In this manner, the data which are received and are temporarily stored in the buffers 185, 186 and 187 can be processed independently, and the efficiency of the data processing can be increased.
Following this, an explanation will be given for the transmission of data from the integrated circuit 100 to the host computer 201. When a single buffer 182 is employed, as is shown in FIG. 21, transmission data are arranged in order in the RAM 181 in accordance with the format defined by the communication protocol, and are transferred to the buffer 182 to be output externally.
When a plurality of buffers are employed, as in FIG. 22, the transmission data are written in the buffers 185, 186 and 187, the number and the size of which are determined in accordance with the format defined by the communication protocol. When the writing is completed, data are read from the buffers 185, 186 and 187 in order, as determined by the format, and are then transmitted.
In the example shown in FIG. 21, where a single buffer is provided for the integrated circuit, in data reception processing, data which are received and temporarily stored in the single buffer are transferred to a memory, such as the RAM, and the data represented by each byte count which is determined in accordance with the communication protocol are interpreted by using software. In data transmission processing, data to be transmitted are arranged in order in the memory, such as a RAM, and are transferred to the buffer.
These conventional methods are effective so long as the format defined by the communication protocol is fixed. However, when there are a plurality of types of transmission and reception formats according to a plurality of communication protocols, it is difficult to change for each format the writing destination and the reading destination in the buffer. And when it is difficult to change the hardware, software must be employed, so that the load imposed on the software is increased and the efficiency of the system processing is deteriorated.
When, as is shown in FIG. 22, a plurality of buffers are provided in an integrated circuit, accordingly, a plurality of sets of buffers are required in order to comply with the plural data format for the plural communication protocols. Thus, as the number of buffers increases, the size of the integrated circuit is likewise increased.
To resolve the above shortcomings, it is one objective of the present invention to provide a system LSI which does not require a periodical writing process using a timer interrupt for an FIFO buffer, and which avoids the condition wherein a communication error occurs.
It is another objective of the present invention to provide an integrated circuit device which imposes a minimum load on software, even when a plurality of formats are defined by communication protocols, and which can perform a process or a setup corresponding to these formats merely by employing a comparatively easy hardware switching process.
To achieve the above objectives, according to the present invention an LSI device comprises:
an FIFO buffer in which transmitting data is written, and from which the transmitting data is output in the order of the writing;
a controller for transmitting the transmitting data to the FIFO buffer in response to a write interrupt signal; and
an FIFO controller for generating and outputting the write interrupt signal to the controller in accordance with a state wherein the FIFO buffer is empty, and for variably setting a variable interval for the write interrupt signal.
According to the present invention, since the FIFO controller can generate the write interrupt signal in accordance with the state wherein the FIFO buffer is empty, and can set a variable interval for the write interrupt signal, an optimal writing process for the system can be implemented, and the frequency at which communication errors occur can be reduced.
When the amount of processing performed by the system is large, the interval allocated for the write interrupt signal is set to be narrowed, and the frequency at which communication errors occur can be reduced. And when the amount of processing performed by the system is small, the interval allocated for the write interrupt signal is set to be expanded and the frequency at which the write interrupt is supplied to the system can be reduced.
In the LSI device according to the above invention, the FIFO controller includes:
a write request generation circuit for generating a first write request signal when the FIFO buffer a first empty state, and for generating a second write-request signal when the FIFO buffer is a second empty state of which the size of the empty area is larger than that in the first empty state; and
a selector for selecting either the first or the second write request signal generated by the write request generation circuit, and for outputting the write interrupt signal which is selected.
According to the present invention, the first and the second write request signals, for which different intervals have been provided, are generated in accordance with the state of the FIFO buffer, and a user can be granted the freedom to select a write request signal having an optimal interval for the system. Therefore, the amount of interrupt processing performed by the system can be optimized, and the frequency of the occurrence of communication errors can be considerably reduced.
Further, in the LSI device of the above invention, the FIFO controller includes an interrupt control circuit for, upon receiving an interrupt permission signal from the controller, permitting or inhibiting the output of the write interrupt signal.
According to the present invention, since the output of the write interrupt signal can be permitted or inhibited in accordance with the interrupt permission signal output by the controller, an optimal transmission process for the system can be performed in accordance with the occurrence of another interrupt in the LSI system and with the priority for the another interrupt.
In the LSI device of the above invention, the write request generation circuit generates the first and the second write request signals in accordance with the relationship existing between a write pointer, for pointing to a write area in the FIFO buffer, and a read pointer, for pointing to a read area in the FIFO buffer.
According to the present invention, a write pointer and a read pointer are employed to generate a plurality of types of write interrupt signals which correspond to the sizes of empty areas.
In the LSI device of the above invention, the interval for the write interrupt signal varies in accordance with the assigned priority for a different interrupt signal which is input to the controller.
According to the present invention, since the interval for the write interrupt signal varies in accordance with the priority assigned to another interrupt signal, which is input to the controller, the interval for a write interrupt signal is dynamically changed in accordance with the processing capabilities of the system. Thus, the frequency at which communication errors occur can be considerably reduced, and the processing efficiency of the entire system can be increased.
In the LSI device of the above invention, when the different interrupt signal having a higher priority than the write interrupt signal, occurs at a first frequency, the selector selects the first write request signal, and when the different interrupt signal occurs at a second frequency lower than the first frequency, the selector selects the second write request signal.
According to the present invention, the selector can select the interval for a write request signal in accordance with the frequency at which an interrupt signal having a higher priority occurs. Therefore, the interval for a write request signal can be dynamically changed in accordance with the processing capabilities of the system, the frequency at which communication errors occur can be considerably reduced, and the processing efficiency of the entire system can be increased.
Further, to achieve the above objectives, an integrated circuit device comprises:
a buffer for temporarily storing transmitting data and received data;
a undivided address setup unit for setting an address for the buffer when the buffer is not divided;
a plurality of sub-buffer address setup units, provided for individual sub-buffers obtained by logically dividing the buffer, for setting addresses for the sub-buffers;
a size setup unit for setting the sizes of the sub-buffers; and
an address setup controller for setting address areas for the sub-buffers in the sub-buffer address setup units in accordance with the sizes of the sub-buffers which is set in the size setup unit, for validating the address in the undivided address setup unit when the buffer is not sub-divided, and for validating the addresses in the undivided address setup unit when the buffer has been sub-divided,
wherein the transmitting data and the received data are written in or read from the undivided buffer in accordance with the address in the undivided address setup unit, and the transmitting data and the received data are written in or read from the sub-buffers in accordance with the addresses from the corresponding sub-buffer address setup units.
According to the present invention, during the transmission or the reception of data the buffer is undivided and can be used as a single buffer for transmitting and receiving the data. On the contrary, when the received data are read from the buffer, or the transmitting data are written in the buffer, the buffer is divided for use as independent sub-buffers whose sizes correspond to the data format for the reading and the writing of data. Further, the buffer can be divided into arbitrary sizes only by setting the sizes of the sub-buffers in the size setup unit. Therefore, the buffer can be divided into sub-buffers in accordance with different data formats, and a flexible structure can be provided for a transmission/reception buffer.
In addition, the integrated circuit device of the above invention further comprises a memory for storing a communication protocol program having a plurality of data formats, wherein the sizes of the sub-buffers are set in the size setup unit in accordance with the respective data formats.
According to the present invention, when there are a plurality of data formats which conform to the communication protocol, so long as the sizes of the sub-buffers are set by the communication protocol program, the transmission/reception buffer can be configured so as to comply to the data formats. Therefore, the buffer can comply to a variety of different data formats flexibly.